Algorithm-based design, through standardization bodies, drives development in the fast moving telecommunications sector. Unfortunately, the pressure to get products to market, restricted budgets and the desire to produce multi-standard platforms rule out application specific integrated circuits (ASICs). To date, the most popular programmable logic choice has been field programmable gate arrays (FPGAs) or digital signal processors (DSPs). Although these devices have enjoyed broad market acceptance, both architectures have inherent limitations that prevent them from scaling to meet high-performance system requirements.

A new category of very high-performance programmable logic devices has been developed to address these unmet needs. The MathStar Field Programmable Object Array (FPOA) is an example of this category, offering field re-programmability, 1 GHz performance, a 400-object array, high-speed I/O, and a streamlined design process. The design methodology of an FPOA leverages the use of building blocks called "objects" rather than "gates" used in an FPGA. This object approach allows an FPOA to operate at 1 GHz, up to four times faster than an FPGA, while still offering all the benefits of a programmable logic device. The FPOA has been developed to provide deterministic, cycle-based timing closure. As opposed to an FPGA, a 1 GHz FPOA will always operate at 1 GHz. The result is a much higher performance solution than those attained within other reprogrammable technologies.

Compare this performance to a DSP-based architecture. A typical DSP may have up to four processing engines that run at speeds of 800 MHz or higher.

DSPs are ultimately limited in performance by their clock rate and the number of useful operations they can do per clock cycle. DSPs can achieve high clock rates, but cannot implement many functions in parallel.

FPGAs, on the other hand, are able to achieve very high levels of parallelization but cannot achieve high clock rates.

It is not uncommon for an FPGA to advertise a maximum clock rate of 500 MHz but only close timing at 200 MHz. This mismatch between advertised clock rate and real life clock rate forces hardware designers to build in plenty of clock frequency headroom when doing an FPGA design. Adding to this headache, the timing closure process is not deterministic and can require many design iterations.

FPOAs, unlike FPGAs which implement most functions at the gate level, employ higher-order building blocks called “objects”. These objects provide a much higher level of abstraction and, therefore, higher performance than the gates of conventional FPGAs. For example, the MathStar Arrix™ family of FPOAs contain over 400 objects that are able to pass data and signals to each other through a configurable communication framework. The timing of both the objects and the communication framework is deterministic at clock rates up to 1 GHz. This deterministic performance eliminates the tedious timing closure design step commonly associated with FPGAs. In addition, the FPOA architecture allows high-level functions, algorithms, equations, and block diagrams to be quickly, directly, and efficiently realized in high-performance silicon.

The current version of the FPOA has three different 1 GHz core objects. The Arithmetic Logic

Unit (ALU) executes logical and mathematical functions on 16-bit data and provides general purpose logic functions for control. The Multiply Accumulator (MAC) performs 16x16 multiply operations with a 40-bit accumulator. The Register File (RF) is a very fast, local memory that can be programmed as RAM, FIFO, or as a sequential read object. These core objects are surrounded by a periphery of internal RAM (IRAM), external DRAM controllers (XRAM) and High-Speed I/O which moves data between core objects and off-chip devices. Communication between all the objects is via a mesh of 21 bit buses guaranteeing a 1 GHz deterministic performance.

MathStar’s Arrix™ family of FPOAs includes 256 ALU objects, 64 MAC objects and 80 RF objects arranged in a 20x20 array as shown in Figure 1 (Click on Image to Enlarge)

Because of its high-performance, the FPOA is useful in a wide range of applications, including those specific for Software Defined Radio, (SDR). These applications are built around extremely fast building blocks, such as Fast Fourier Transform (FFT), Finite Impulse Response (FIR) filters, Digital Down Converters (DDC), Digital Up Converters (DUC), and Turbo Decoding.

A couple of these will be used to highlight the FPOA’s capabilities.

The FFT is an ingenious algorithm that is used for applications that require a discrete signal to be converted from the time to the frequency domain. The performance metrics of an FFT include the number of bits used to represent each sample, the number of samples, or points, in the FFT representation, and the rate at which the FFT can handle new inputs, also known as the sample rate. The FPOA architecture is ideal for FFTs with sample rates up to 1 Giga sample per second (Gsps), many times the performance of an FPGA. Table 1 shows performance benchmarks for various FFTs.

The major parts of any Digital Up/Down Converter are the Numerically Controlled Oscillator (NCO), mixer and filters. To produce an accurate 16-bit NCO, with 500MHz issue rates, all that is required is 1 MAC, 7 ALU and 2 RF objects.. FIR filters are also very easy to realize with variable degrees of flexibility. This allows full optimization of the filter to the physical requirements of the SDR. Table 2 shows maximum performance benchmarks for various FIR configurations.

The FPOA represents the next generation of programmable logic, addressing high-performance embedded applications such as SDR’s. The FPOA combines massively parallel computation found in FPGAs with the 1 GHz clock rates found in DSPs. For applications such as FFTs, FIRs, DDCs etc, the FPOA represents up to four times the performance of large FPGAs in a single chip solution. Moving into the next generation of radio systems will introduce further complexity of algorithm such as MIMO. Here combining channels back at the receiver will require significant processing power to compute what are, in essence, multiple simultaneous equations. The FPOA gives the processing power to perform these complex matrix decompositions.

Peter Trott
EMEA Field Applications Engineer
Mathstar